The dynamics of chaotic memristor-based systems offer promising potential for secure communication.However,existing solutions frequently suffer from drawbacks such as slow synchronization,low key diversity,and poor no...The dynamics of chaotic memristor-based systems offer promising potential for secure communication.However,existing solutions frequently suffer from drawbacks such as slow synchronization,low key diversity,and poor noise resistance.To overcome these issues,a novel fractional-order chaotic system incorporating a memristor emulator derived from the Shinriki oscillator is proposed.The main contribution lies in the enhanced dynamic complexity and flexibility of the proposed architecture,making it suitable for cryptographic applications.Furthermore,the feasibility of synchronization to ensure secure data transmission is demonstrated through the validation of two strategies:an active control method ensuring asymptotic convergence,and a finite-time control method enabling faster stabilization.The robustness of the scheme is confirmed by simulation results on a color image:χ^(2)=253/237/267(R/G/B);entropy≈7.993;correlations between adjacent pixels in all directions are close to zero(e.g.,-0.0318 vertically);and high number of pixel change rate and unified average changing intensity(e.g.,33.40%and 99.61%,respectively).Peak signal-to-noise ratio analysis shows that resilience to noise and external disturbances is maintained.It is shown that multiple fractional orders further enrich the chaotic behavior,increasing the systems suitability for secure communication in embedded environments.These findings highlight the relevance of fractional-order chaotic memristive systems for lightweight secure transmission applications.展开更多
文摘The dynamics of chaotic memristor-based systems offer promising potential for secure communication.However,existing solutions frequently suffer from drawbacks such as slow synchronization,low key diversity,and poor noise resistance.To overcome these issues,a novel fractional-order chaotic system incorporating a memristor emulator derived from the Shinriki oscillator is proposed.The main contribution lies in the enhanced dynamic complexity and flexibility of the proposed architecture,making it suitable for cryptographic applications.Furthermore,the feasibility of synchronization to ensure secure data transmission is demonstrated through the validation of two strategies:an active control method ensuring asymptotic convergence,and a finite-time control method enabling faster stabilization.The robustness of the scheme is confirmed by simulation results on a color image:χ^(2)=253/237/267(R/G/B);entropy≈7.993;correlations between adjacent pixels in all directions are close to zero(e.g.,-0.0318 vertically);and high number of pixel change rate and unified average changing intensity(e.g.,33.40%and 99.61%,respectively).Peak signal-to-noise ratio analysis shows that resilience to noise and external disturbances is maintained.It is shown that multiple fractional orders further enrich the chaotic behavior,increasing the systems suitability for secure communication in embedded environments.These findings highlight the relevance of fractional-order chaotic memristive systems for lightweight secure transmission applications.
