Abstract:Approximate computing has received significant attention in the design of portable CMOS hardware for error-tolerant applications.This work proposes an approximate adder that to optimize area delay and achieve...Abstract:Approximate computing has received significant attention in the design of portable CMOS hardware for error-tolerant applications.This work proposes an approximate adder that to optimize area delay and achieve energy efficiency using Parallel Carry(PC)generation logic.For‘n’bits in input,the proposed algorithm use approximate addition for least n/2 significant bits and exact addition for most n/2 significant bits.A simple OR logic with no carry propagation is used to implement the approximate part.In the exact part,addition is performed using 4-bit adder blocks that implement PC at block level to reduce node capacitance in the critical path.Evaluations reveal that the maximum error of the proposed adder confines not more than 2n/2.As an enhancement of the proposed algorithm,we use the Error Recovery(ER)module to reduce the average error.Synthesis results of Proposed-PC(P-PC)and Proposed-PCER(P-PCER)adders with n-16 in 180nm Application Specific Integrated Circuit(ASIC)PDK technology revealed 44.2%&41.7%PDP reductions and 43.4%&40.7%ADP reductions,respectively compared to the latest best approximate design compared.The functional and driving effectiveness of proposed adders are examined through digital image processing applications.展开更多
文摘Abstract:Approximate computing has received significant attention in the design of portable CMOS hardware for error-tolerant applications.This work proposes an approximate adder that to optimize area delay and achieve energy efficiency using Parallel Carry(PC)generation logic.For‘n’bits in input,the proposed algorithm use approximate addition for least n/2 significant bits and exact addition for most n/2 significant bits.A simple OR logic with no carry propagation is used to implement the approximate part.In the exact part,addition is performed using 4-bit adder blocks that implement PC at block level to reduce node capacitance in the critical path.Evaluations reveal that the maximum error of the proposed adder confines not more than 2n/2.As an enhancement of the proposed algorithm,we use the Error Recovery(ER)module to reduce the average error.Synthesis results of Proposed-PC(P-PC)and Proposed-PCER(P-PCER)adders with n-16 in 180nm Application Specific Integrated Circuit(ASIC)PDK technology revealed 44.2%&41.7%PDP reductions and 43.4%&40.7%ADP reductions,respectively compared to the latest best approximate design compared.The functional and driving effectiveness of proposed adders are examined through digital image processing applications.
