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A cryogenic 3.3-V supply,1.6% 3σ-accuracy all-CMOS voltage reference with 58-dB PSR@10 kHz in 0.18-μm CMOS
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作者 Yupeng Yuan Yi Zhuo +5 位作者 jianjun tu Qingjiang Xia Yan Zhang Wengao Lu Xiangyang Li Ding Ma 《Journal of Semiconductors》 2025年第8期30-35,共6页
This brief presents a cryogenic voltage reference circuit designed to operate effectively across a wide temperature range from 30 to 300 K.A key feature of the proposed design is utilizing a current subtraction techni... This brief presents a cryogenic voltage reference circuit designed to operate effectively across a wide temperature range from 30 to 300 K.A key feature of the proposed design is utilizing a current subtraction technique for temperature compensation of the reference current,avoiding the deployment of bipolar transistors to reduce area and power consumption.Implemented with a 0.18-μm CMOS process,the circuit achieves a temperature coefficient(TC)of 67.5 ppm/K,which was not achieved in previous works.The design can also attain a power supply rejection(PSR)of 58 d B at 10 k Hz.Meanwhile,the average reference voltage is 1.2 V within a 1.6%3σ-accuracy spread.Additionally,the design is characterized by a minimal power dissipation of 1μW at 30 K and a compact chip area of 0.0035 mm~2. 展开更多
关键词 voltage reference TC compensation high accuracy cryogenic CMOS MOS-based extreme environment
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