In this paper, the authors design a novel chaotic secure communication system, which has high security and good error correcting capability. Firstly, the Henon Chaos Shift Keying (CSK) modulation block is presented. S...In this paper, the authors design a novel chaotic secure communication system, which has high security and good error correcting capability. Firstly, the Henon Chaos Shift Keying (CSK) modulation block is presented. Secondly, chaotic turbo encoder/decoder (hard decision) is introduced. Thirdly, this chaotic secure communication system, which comprises the Henon CSK modulation block and chaotic turbo encoder in a serially concatenated form, is shown. Furthermore, a novel two step encryption scheme is proposed, which is based on the chaotic turbo encoded Henon CSK secure communication system.展开更多
A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarith...A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.展开更多
A novel product code iterative decoding algorithm and its high speed implementation scheme are proposed in this paper. Based on partial combination of selected columns of check matrix, the reduced-complexity syndrome ...A novel product code iterative decoding algorithm and its high speed implementation scheme are proposed in this paper. Based on partial combination of selected columns of check matrix, the reduced-complexity syndrome decoding method is proposed to decode sub-codes of product code and deliver soft output information. So iterative decoding of product codes is possible. The fast sorting algorithm and a look-up method are proposed for high speed implementation of this algorithm. Compared to the conventional weighing iterative algorithm, the proposed algorithm has lower complexity while offering better performance, which is demonstrated by simulations and implementation analysis. The implementation scheme and verilog HDL simulation show that it is feasible to achieve high speed decoding with the proposed algorithm.展开更多
Factor graph, so named because it graphically represents function factorization, with which and its sum-product algorithm the iterative algorithm can be derived clearly. An iterative multiuser receiver based on factor...Factor graph, so named because it graphically represents function factorization, with which and its sum-product algorithm the iterative algorithm can be derived clearly. An iterative multiuser receiver based on factor graph for asynchronous coded CDMA system is proposed. In this paper, the a posteriori probability of users information bits conditioned on the noise-whitening filters output is represented by factor graphs, after numbers of iterations with the sum-product algorithm the information bits are estimated. The authors also propose a reduced complexity algorithm. Simulation results show that with this proposed receiver, near-single-user performance can be achieved, and small performance degradation for the reduced complexity algorithm with significant complexity reduction.展开更多
文摘In this paper, the authors design a novel chaotic secure communication system, which has high security and good error correcting capability. Firstly, the Henon Chaos Shift Keying (CSK) modulation block is presented. Secondly, chaotic turbo encoder/decoder (hard decision) is introduced. Thirdly, this chaotic secure communication system, which comprises the Henon CSK modulation block and chaotic turbo encoder in a serially concatenated form, is shown. Furthermore, a novel two step encryption scheme is proposed, which is based on the chaotic turbo encoded Henon CSK secure communication system.
文摘A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.
基金the National Natural Science Foundation of China.
文摘A novel product code iterative decoding algorithm and its high speed implementation scheme are proposed in this paper. Based on partial combination of selected columns of check matrix, the reduced-complexity syndrome decoding method is proposed to decode sub-codes of product code and deliver soft output information. So iterative decoding of product codes is possible. The fast sorting algorithm and a look-up method are proposed for high speed implementation of this algorithm. Compared to the conventional weighing iterative algorithm, the proposed algorithm has lower complexity while offering better performance, which is demonstrated by simulations and implementation analysis. The implementation scheme and verilog HDL simulation show that it is feasible to achieve high speed decoding with the proposed algorithm.
基金the National Science Foundation of China and Key Subject Project of the Ministry of Education.
文摘Factor graph, so named because it graphically represents function factorization, with which and its sum-product algorithm the iterative algorithm can be derived clearly. An iterative multiuser receiver based on factor graph for asynchronous coded CDMA system is proposed. In this paper, the a posteriori probability of users information bits conditioned on the noise-whitening filters output is represented by factor graphs, after numbers of iterations with the sum-product algorithm the information bits are estimated. The authors also propose a reduced complexity algorithm. Simulation results show that with this proposed receiver, near-single-user performance can be achieved, and small performance degradation for the reduced complexity algorithm with significant complexity reduction.
