系统级封装(System in Packet,SiP)技术将多个子系统集成在一个封装内,具有组装方式灵活、研发周期短等优势,在电子设备小型化的进程中具有广阔的发展前景.在SiP的设计流程中,原理图设计是否正确往往决定了整体设计的成败.然而,原理图...系统级封装(System in Packet,SiP)技术将多个子系统集成在一个封装内,具有组装方式灵活、研发周期短等优势,在电子设备小型化的进程中具有广阔的发展前景.在SiP的设计流程中,原理图设计是否正确往往决定了整体设计的成败.然而,原理图设计中出现的连接性错误通常需要工程人员花费大量时间进行查找对比,从而确定错误的位置.为了提高原理图连接性错误检查的效率,提出了一种应用于SiP系统级封装原理图设计阶段的连接性规则检查错误反标工具,由工具命令语言(Tool Command Language,TCL)开发.该工具以插件形式集成于OrCAD Capture CIS X具中,可以配合已有的原理图规则检查工具,使用户可以通过图形界面获取并分析规则检查工具生成的有效错误信息,并将错误信息清晰直观的反标于原理图的相应位置.通过对由26页原理图组成的测试系统进行错误反标测试,该工具可以在数秒内将原理图中的连接性错误信息反标在原理图的对应位置,使设计人员可以快速定位错误的位置,有效的提高了原理图设计阶段连接性检查的效率.展开更多
With its growth in spacecraft control applications,the microcontroller(MCU)becomes increasingly sensitive to radiation and the risks of system failure.In a radiation environment,the MCU is vulnerable to impacts from h...With its growth in spacecraft control applications,the microcontroller(MCU)becomes increasingly sensitive to radiation and the risks of system failure.In a radiation environment,the MCU is vulnerable to impacts from high-energy particles,which can lead to single-event effect(SEE)that disrupt normal system operations.The pipeline of MCU,being the core structure of the system,is particularly susceptible to single-event upset(SEU)and potentially causes execution failures.However,existing radiation-hardening techniques offer limited effectiveness for pipelines.To enhance SEU resistance,this study focused on a 32-bit MCU core with eight pipeline stages,proposing a pipeline hardening approach that utilizes lockstep technology to improve fault tolerance.Signals from two processors were compared including register write data,register contents and pre-fetched instructions.Any discrepancies triggered error flags to indicate faults.When an error flag was raised,recovery was initiated through an interrupt.The interrupt handler then retrieved state information from the advanced peripheral bus(APB)slave module to restore the CPU's operational state and resume execution.By combining hardware-based state preservation with software-driven error recovery,the proposed solution demonstrated significant improvements in fault tolerance rates and performance compared to traditional checkpoint-based techniques.After completing the pipeline hardening design,a fault injection platform was utilized in this paper to simulate real-world error conditions on internal processor modules.The platform was developed based on the circuit's register-transfer-level(RTL)design and statistical results.The fault injection platform was performed by automatically finding all registers within the target design.The register values were forced to upset at the tens of nanoseconds scale in the RTL description of the circuit's design.After running the circuit's functional simulation,the statistics of the faults in registers were displayed on the platform,which evaluated the influence of SEU.The vulnerability of SEU in the circuit could be observed from the results of the soft error statistics.The post-hardening soft error rates were then measured and compared to pre-hardening data,providing a quantitative evaluation of the improvements.Using this method,the soft error rates of the modules in the MCU core such as PFU,DPU,and Cache AXIM are 40.07%,26.36%,and 27.29%respectively before hardening.The soft error rates of modules mentioned above are reduced to 0%,0.69%,and 1.11%after hardening.The hardened and non-hardened designs of the entire core were implemented in FPGA.The total resource utilization of the triple mode redundancy(TMR)is 111984,as indicated by the number of look-up tables(LUTs)and registers consumed in the FPGA.The total resource utilization of this work is 78034,and the ratio of resource utilization between this work and TMR is approximately 69.68%.The error recovery time for the hardened MCU processor was analyzed using the completion cycles of a bubble sort algorithm as a benchmark.In this paper,the average recovery cycle using the software checkpoint roll-back method is 36479.06,and the average recovery cycle using this work is 26922.5.The ratio of recovery cycles between this work and checkpoint roll-back is about 73.8%.Assessments through random fault injection and FPGA implementation indicate that this approach effectively reduces processor faults caused by soft errors while optimizing resource utilization and efficiency over triplemodular redundancy.展开更多
文摘With its growth in spacecraft control applications,the microcontroller(MCU)becomes increasingly sensitive to radiation and the risks of system failure.In a radiation environment,the MCU is vulnerable to impacts from high-energy particles,which can lead to single-event effect(SEE)that disrupt normal system operations.The pipeline of MCU,being the core structure of the system,is particularly susceptible to single-event upset(SEU)and potentially causes execution failures.However,existing radiation-hardening techniques offer limited effectiveness for pipelines.To enhance SEU resistance,this study focused on a 32-bit MCU core with eight pipeline stages,proposing a pipeline hardening approach that utilizes lockstep technology to improve fault tolerance.Signals from two processors were compared including register write data,register contents and pre-fetched instructions.Any discrepancies triggered error flags to indicate faults.When an error flag was raised,recovery was initiated through an interrupt.The interrupt handler then retrieved state information from the advanced peripheral bus(APB)slave module to restore the CPU's operational state and resume execution.By combining hardware-based state preservation with software-driven error recovery,the proposed solution demonstrated significant improvements in fault tolerance rates and performance compared to traditional checkpoint-based techniques.After completing the pipeline hardening design,a fault injection platform was utilized in this paper to simulate real-world error conditions on internal processor modules.The platform was developed based on the circuit's register-transfer-level(RTL)design and statistical results.The fault injection platform was performed by automatically finding all registers within the target design.The register values were forced to upset at the tens of nanoseconds scale in the RTL description of the circuit's design.After running the circuit's functional simulation,the statistics of the faults in registers were displayed on the platform,which evaluated the influence of SEU.The vulnerability of SEU in the circuit could be observed from the results of the soft error statistics.The post-hardening soft error rates were then measured and compared to pre-hardening data,providing a quantitative evaluation of the improvements.Using this method,the soft error rates of the modules in the MCU core such as PFU,DPU,and Cache AXIM are 40.07%,26.36%,and 27.29%respectively before hardening.The soft error rates of modules mentioned above are reduced to 0%,0.69%,and 1.11%after hardening.The hardened and non-hardened designs of the entire core were implemented in FPGA.The total resource utilization of the triple mode redundancy(TMR)is 111984,as indicated by the number of look-up tables(LUTs)and registers consumed in the FPGA.The total resource utilization of this work is 78034,and the ratio of resource utilization between this work and TMR is approximately 69.68%.The error recovery time for the hardened MCU processor was analyzed using the completion cycles of a bubble sort algorithm as a benchmark.In this paper,the average recovery cycle using the software checkpoint roll-back method is 36479.06,and the average recovery cycle using this work is 26922.5.The ratio of recovery cycles between this work and checkpoint roll-back is about 73.8%.Assessments through random fault injection and FPGA implementation indicate that this approach effectively reduces processor faults caused by soft errors while optimizing resource utilization and efficiency over triplemodular redundancy.
