High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform(FFT)application,such as Synthetic Aperture Radar(SAR)processing and medical imaging.In SAR processing,the image size could b...High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform(FFT)application,such as Synthetic Aperture Radar(SAR)processing and medical imaging.In SAR processing,the image size could be 4 k×4 k in normal and it has become larger over the years.In the view of real-time,extensibility and reusable characteristics,an Field Programmable Gate Array(FPGA)based multi-channel variable-length FFT architecture which adopts radix-2 butterfly algorithm is proposed in this paper.The hardware implementation of FFT is partially reconfigurable architecture.Firstly,the proposed architecture in the paper has flexibility in terms of chip area,speed,resource utilization and power consumption.Secondly,the proposed architecture combines serial and parallel methods in its butterfly computations.Furthermore,on system-level issue,the proposed architecture takes advantage of state processing in serial mode and data processing in parallel mode.In case of sufficient FPGA resources,state processing of serial mode mentioned above is converted to pipeline mode.State processing of pipeline mode achieves high throughput.展开更多
基金The work was supported by National Natural Science Foundation of China(61271149)and by Beijing Natural Science Foundation(4144093)
文摘High-speed real-time digital frequency analysis is one major field of Fast Fourier Transform(FFT)application,such as Synthetic Aperture Radar(SAR)processing and medical imaging.In SAR processing,the image size could be 4 k×4 k in normal and it has become larger over the years.In the view of real-time,extensibility and reusable characteristics,an Field Programmable Gate Array(FPGA)based multi-channel variable-length FFT architecture which adopts radix-2 butterfly algorithm is proposed in this paper.The hardware implementation of FFT is partially reconfigurable architecture.Firstly,the proposed architecture in the paper has flexibility in terms of chip area,speed,resource utilization and power consumption.Secondly,the proposed architecture combines serial and parallel methods in its butterfly computations.Furthermore,on system-level issue,the proposed architecture takes advantage of state processing in serial mode and data processing in parallel mode.In case of sufficient FPGA resources,state processing of serial mode mentioned above is converted to pipeline mode.State processing of pipeline mode achieves high throughput.
