In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square v...In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size.The TDC has a dead time of about 200 ns while the dynamic range is 655.36 μs.The double delay lines method is employed to cut the dead time in half to improve its performance.As the bin size of the TDC is dependent on temperature,a compensation algorithm is adopted as temperature drift correction,and the TDC shows satisfying performance in a temperature range from –5℃ to +55℃.展开更多
基金Supported by State Key Program of National Natural Science of China under Grant No.11079003Fundamental Research Funds for the Central Universities(No.WK2030040023,and WK2030040015)
文摘In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size.The TDC has a dead time of about 200 ns while the dynamic range is 655.36 μs.The double delay lines method is employed to cut the dead time in half to improve its performance.As the bin size of the TDC is dependent on temperature,a compensation algorithm is adopted as temperature drift correction,and the TDC shows satisfying performance in a temperature range from –5℃ to +55℃.
