In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square v...In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size.The TDC has a dead time of about 200 ns while the dynamic range is 655.36 μs.The double delay lines method is employed to cut the dead time in half to improve its performance.As the bin size of the TDC is dependent on temperature,a compensation algorithm is adopted as temperature drift correction,and the TDC shows satisfying performance in a temperature range from –5℃ to +55℃.展开更多
The impact of the integral non-linearity (INL) to the time resolution of HPTDC (High Performance Time to Digital Converter) is presented in this paper.An INL correction method based on look-up table (LUT),is proposed ...The impact of the integral non-linearity (INL) to the time resolution of HPTDC (High Performance Time to Digital Converter) is presented in this paper.An INL correction method based on look-up table (LUT),is proposed to minimize such INL and improve the time resolution.This scheme is implemented in a single Field Programmable Gate Array (FPGA) device for real-time compensation.The INL characteristic estimation is based on a statistical approach,in which a sufficiently large number of random input signals are measured.The prototype tests show that the deviation for time resolution due to INL can be reduced greatly,from more than 80 ps to less than 20 ps,which can meet the requirement of BES (Beijing Spectrometer) III Time-Of-Flight detector.展开更多
基金Supported by State Key Program of National Natural Science of China under Grant No.11079003Fundamental Research Funds for the Central Universities(No.WK2030040023,and WK2030040015)
文摘In this paper,a high precision vernier delay line(VDL) TDC(Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented,achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size.The TDC has a dead time of about 200 ns while the dynamic range is 655.36 μs.The double delay lines method is employed to cut the dead time in half to improve its performance.As the bin size of the TDC is dependent on temperature,a compensation algorithm is adopted as temperature drift correction,and the TDC shows satisfying performance in a temperature range from –5℃ to +55℃.
基金Supported by BEPCII project (BEPC II-UDDETF-309-HT182/2004)Knowledge Innovation Program of The Chinese Academy of Sciences (YFKJCX3. SYW. N5)the National Natural Science Foundation of China (No.10970033)
文摘The impact of the integral non-linearity (INL) to the time resolution of HPTDC (High Performance Time to Digital Converter) is presented in this paper.An INL correction method based on look-up table (LUT),is proposed to minimize such INL and improve the time resolution.This scheme is implemented in a single Field Programmable Gate Array (FPGA) device for real-time compensation.The INL characteristic estimation is based on a statistical approach,in which a sufficiently large number of random input signals are measured.The prototype tests show that the deviation for time resolution due to INL can be reduced greatly,from more than 80 ps to less than 20 ps,which can meet the requirement of BES (Beijing Spectrometer) III Time-Of-Flight detector.
