A low-power,high-speed dynamic comparator with the addition of a cross-coupled pair in the pre-amplifier stage,followed by a strong-arm latch,is presented.The proposed modification increases the pre-amplifier’s diffe...A low-power,high-speed dynamic comparator with the addition of a cross-coupled pair in the pre-amplifier stage,followed by a strong-arm latch,is presented.The proposed modification increases the pre-amplifier’s differential and common-mode gains,improving the latch’s differential and common-mode input voltage,resulting in faster regeneration with 22%speed improvement as compared to conventional comparator at small input differential voltages(V_(i,id)).The proposed technique boosts the comparator’s speed and helps achieve 21%lower energy per conversion delay product(EDP)compared to the literature.Analytical modeling of the delay that proves the improvement in the speed of the proposed comparator is also presented and verified with the simulation results.The proposed comparator’s delay is insensitive to the common-mode voltage(V_(i,cm)).The proposed comparator is fabricated in 180-nm CMOS technology and measurement shows less than 160 ps relative CLK-Q delay with 81 fJ.ns EDP and 0.8 mV input-referred rms noise with 1.8 V supply.To demonstrate the scalability of the proposed technique to advanced technology nodes,the proposed design is also simulated in 65-nm CMOS technology with a 1.1 V supply for 5 GHz frequency.For V_(i,cm) of 0.3 V and V_(i,id) of 1 mV and 10 mV,the proposed comparator exhibits a 40.69 ps and 32.41 ps delay and has 3.74 fJ.ns and 2.78 fJ.ns EDP respectively.展开更多
基金supported by the Anusandhan National Research Foundation of India under Grant CRG/2021/007283 for Tapeout and MeitY(C2S programme).
文摘A low-power,high-speed dynamic comparator with the addition of a cross-coupled pair in the pre-amplifier stage,followed by a strong-arm latch,is presented.The proposed modification increases the pre-amplifier’s differential and common-mode gains,improving the latch’s differential and common-mode input voltage,resulting in faster regeneration with 22%speed improvement as compared to conventional comparator at small input differential voltages(V_(i,id)).The proposed technique boosts the comparator’s speed and helps achieve 21%lower energy per conversion delay product(EDP)compared to the literature.Analytical modeling of the delay that proves the improvement in the speed of the proposed comparator is also presented and verified with the simulation results.The proposed comparator’s delay is insensitive to the common-mode voltage(V_(i,cm)).The proposed comparator is fabricated in 180-nm CMOS technology and measurement shows less than 160 ps relative CLK-Q delay with 81 fJ.ns EDP and 0.8 mV input-referred rms noise with 1.8 V supply.To demonstrate the scalability of the proposed technique to advanced technology nodes,the proposed design is also simulated in 65-nm CMOS technology with a 1.1 V supply for 5 GHz frequency.For V_(i,cm) of 0.3 V and V_(i,id) of 1 mV and 10 mV,the proposed comparator exhibits a 40.69 ps and 32.41 ps delay and has 3.74 fJ.ns and 2.78 fJ.ns EDP respectively.
