摘要
Implementing check node(CN)update based on the minimum value(MV)and second MV of incoming message magnitudes is crucial for Min-Sum Algorithms(MSAs).In the category of bit-serial implementations,existing schemes suffer from decoding performance degradation,large hardware areas,and/or long latency.In this paper,we propose two efficient CN update functions based on the MV and an approximate second MV,and design bit-serial architectures to implement them.Simulation results show that our functions exhibit the minimum decoding performance degradation compared to the existing functions using approximate second MVs.Moreover,the applicationspecific integrated circuits(ASIC)implementation results demonstrate the advantages of our architectures in terms of area,latency,etc.
基金
supported by National Natural Science Foundation of China(NSFC)under Grant 62571455,Grant 62371401,and Grant 62331002
supported by the SingaporeMinistry of Education Academic Research Fund Tier 2 T2EP50221-0036.
