摘要
本研究分析并建模了一个采用28纳米工艺的5路时间交织逐次逼近寄存器型(TI-SAR)模数转换器(ADC),重点展示了利用混合信号行为模型进行的架构探索。建模中讨论了比较器噪声与失调、电容失配、时序偏差等非理想因素,量化分析了各非理想因素对ADC核心性能的贡献占比。研究测试了一种基于比较器失调窗口识别和平均绝对偏差(MAD)的偏差校正方法以减少交织误差,针对该方法的校准精度、收敛速度、功耗开销进行了系统性测试,并与现有主流校准方法开展定量对比。仿真结果显示,信噪失真比(SNDR)为40 dB,无杂散动态范围(SFDR)为56.1 dB,品质因数(FoM)为34.87 fJ/conv-step,通过误差溯源分析,明确了核心性能指标与设计目标存在差距的主要成因为高阶时序偏差未完全补偿、多通道电容失配耦合效应及比较器热噪声叠加,并据此提出了分层补偿的针对性优化思路。本文提供了时序偏差的完整理论分析,设计了专门的对比分析模块,从校准精度、收敛速度、功耗开销、FoM等维度将所提方法与先进研究进行定量对比,清晰体现了算法的创新点与工程优势。局限性包括缺乏数字实现与硬件成本评估,本文对各局限性的核心难点进行了深入剖析,并制定了分阶段、可落地的后续研究具体规划。本研究为后续电路实现提供了基础系统分析与优化方向。
This study analyzes and models a 5-channel time-interleaved successive approximation register(TI-SAR)analog-to-digital converter(ADC)fabricated with a 28-nanometer process,with a focus on architectural exploration using a mixed-signal behavioral model.Non-ideal factors including comparator noise and offset,capacitor mismatch,and timing skew are discussed in the modeling process,and the contribution ratio of each non-ideal factor to the core performance of the ADC is quantitatively analyzed.A skew correction method based on comparator offset window identification and mean absolute deviation(MAD)is investigated to mitigate interleaving errors,for which systematic tests on calibration accuracy,convergence speed and power consumption overhead are conducted,along with a quantitative comparison against the mainstream existing calibration methods.Simulation results show that the signal-to-noise and distortion ratio(SNDR)reaches 40 dB,the spurious-free dynamic range(SFDR)is 56.1 dB,and the figure of merit(FoM)is 34.87 fJ/conv-step.Through error source tracing and analysis,the primary causes for the gap between the core performance indicators and the design targets are identified as the incomplete compensation of high-order timing skew,the coupling effect of multi-channel capacitor mismatch,and the superposition of comparator thermal noise.Corresponding targeted optimization ideas based on hierarchical compensation are proposed accordingly.This paper presents a complete theoretical analysis of timing skew and designs a dedicated comparative analysis module to conduct a quantitative comparison of the proposed method with state-of-the-art research from the perspectives of calibration accuracy,convergence speed,power consumption overhead and FoM,which clearly demonstrates the innovative points and engineering advantages of the proposed algorithm.The limitations of this study include the lack of digital implementation and hardware cost evaluation of the calibration algorithm;this paper conducts an in-depth analysis of the core difficulties of each limitation and formulates a phased and feasible specific plan for subsequent research.This work provides a fundamental system analysis and optimization directions for subsequent circuit implementation.
作者
程旭
张霖
Xu Cheng;Zhang Lin(School of Electronic,Electrical Engineering and Physics,Fujian University of Technology,Fuzhou,350118,China)
出处
《信息化研究》
2026年第1期78-86,共9页
INFORMATIZATION RESEARCH
关键词
逐次逼近寄存器型模数转换器
时间交织模数转换器
后台校准
时序偏差
失调校准
平均绝对偏差
误差溯源
性能优化
算法对比
SAR analog-to-digital converter
time-interleaved analog-to-digital converter
background calibration
timing skew
offset calibration
mean absolute deviation
error source tracing
performance optimization
algorithm comparison
