摘要
This paper introduces aΔ-Σfractional output divider(FOD)designed for audio system-on-chip(SoC)applications with low design and implementation cost.In contrast to conventional FOD design methodologies that utilize a multi-modulus divider(MMD)or a multi-phase multiplexer(MPM)based divider incorporating complex jitter filters,the proposed FOD adopts a feed-forward architecture employing simple circuit building blocks.It leverages aΔ-Σdigital-to-frequency converter(DFC)to generate fractionally synthesized output frequencies,eliminating the synchronous constraint associated with MMD and MPM methods.The DFC employs a fully-synthesizableΔ-Σmodulator and resistor-2 resistor(R-2R)digital-to-analog converter to generate 4-level waveform patterns containing the desired output frequency information.These patterns are then processed through an integrator and a zero-crossing detector to reconstruct the fractionally divided output clock signal.Furthermore,to minimize jitter,a simple edge combiner-based jitter filter is cascaded with the DFC output.Implemented in 180 nm digital complementary metal-oxide-semiconductor process and operating at 1.2 V supply voltage,the proposed FOD offers an output frequency range of 500 kHz to 45 MHz,with N_(min)=F_(IN)/F_(OUT)=4.Specifically,It divides a 26 MHz input to generate a 6.144 MHz(128fs=128×44.1 kHz)output,exhibiting a root-mean-square jitter of 3.68 ps,while consuming 0.22 mW of power.
基金
supported partially by the National Science and Technology Major Project(No.2022ZD0115800)
the“Tianshan Talents”Training Program for Outstanding Engineer(No.TS240007)
Shihezi University International Science and Technology Cooperation Promotion Project(No.GJHZ202106).
