摘要
为解决NAND闪存控制器的构架设计和硬件测试问题,提出了一种NAND闪存控制器的设计方案,搭建了基于上位机控制的高效硬件测试平台。该构架基于ZYNQ软核,通过GPIO总线将来自上位机的操作命令和数据传输给控制器,然后控制器产生控制信号给芯片;该测试平台基于ONFI 3. 2协议,利用LDO实现Vcc和Vccq的电压开启要求,达到Flash芯片开启条件。在充分仿真验证控制器时序、功能的基础上,利用搭建的硬件测试平台进行板级验证。最终结果表明,所提方案能够满足NAND闪存驱动控制要求。
In order to solve the architecture design and hardware testing problems of NAND Flash memory controllers,a design scheme of NAND flash controller and an efficient hardware testing platform with the control of a host computer were proposed.The architecture is based on the ZYNQ soft core.The operating commands and data from the host computer are transmitted to the controller through the General Purpose Input Output(GPIO)bus,then the controller generates the control signal to the chip.The test platform is based on the ONFI 3.2 protocol,and the voltage of the Vcc and Vccq are turned on using the Low Dropout Regulator(LDO)and achieve the flash chip open conditions.On the basis of full simulation of the timing and function of the controller,the board level verification was performed using the hardware platform.The result shows that this design can meet the control requirements of NAND Flash driver.
作者
王柯
姜一扬
张黄鹏
姜丹丹
WANG Ke;JIANG Yiyang;ZHANG Huangpeng;JIANG Dandan(College of Communication Engineering,Chendu University of Information Technology,Chengdu Sichuan 610225,China;School of Electronic,Electrical and Communication Engineering,University of Chinese Academy of Sciences,Beijing 100049,China;Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China)
出处
《计算机应用》
CSCD
北大核心
2018年第A02期254-257,共4页
journal of Computer Applications
