摘要
提出了一种结构简单、采用有源衰减器的低压ＣＭＯＳ四象限模拟乘法器。详细分析了电路的结构和设计原理，给出了电路的ＰＳＰＩＣＥ模拟结果。模拟结果表明，当电源电压为±１．５Ｖ时，功耗小于８０μＷ，线性输入电压范围约为±０．５Ｖ；当输入电压范围限于±０．３Ｖ时，非线性误差小于１．３％；－３ｄＢ带宽约为３．２ＭＨｚ。该乘法器电路可应用于低压模拟信号处理电路中。
A simple low voltage CMOS four quadrant analog multiplier using active
attenuators is presented. Its basic configuration and design principle are analyzed.
Results from PSPICE simulation show that the circuit has a power dissipation of 80 μ
W and a full scale linear input range about ±0.5 V for ±1.5 V power supply. The
nonlinear error of the multiplier is less than 1.3% with an input rang up to ±0.3 V ,
and the simulated -3 dB bandwidth is about 3.2 MHz . The proposed multiplier is
very useful in low voltage analog signal processing applications.
出处
《微电子学》
CAS
CSCD
北大核心
1999年第3期211-214,219,共5页
Microelectronics
