摘要
为了提高数据采集卡的速度,同时降低成本,设计一种并行数据采集系统,要求并行采集速度大于10 Mb/s。整个系统由AVR与CPLD控制实现,通过MAX1308完成模数转换,并设计搭建了其外围电路。采用12路数据存储模式存储高速采集的数据。实验依据存储要求搭建硬件电路并调试,示波器显示的波形结果8组脉冲序列完全对齐,没有出现时序混乱,同时并行处理过程中不相互影响,实现了低成本高速多路采集的设计要求。
In order to improve the speed of data acquisition card, while reducing costs, the parallel data acquisition system is designed, which requires a parallel acquisition speed is greater than 10Mb/s. The system consists of AVR and the CPLD control implementation, through a MAXI308 ADC completion of the transformation process, and is designed to build its peripheral circuits. Using a 12-channel data storage mode for high-speed data acquisition storage, experimental basis for the storage requirements to build and debug the hardware circuit, the oscilloscope waveform displays the results of pulse sequences of their eight groups, there was no temporal chaos in parallel processing, and does not interact to achieve a low-cost high-speed multi-channel acquisition design requirements.
出处
《电子设计工程》
2010年第7期161-163,共3页
Electronic Design Engineering
基金
山西省自然科学基础(2007012003)资助项目
