摘要
文中运用信息论原理对多值“加法型”组合生成器序列进行分析，得到钟控序列与输出序列的互信息为零的结论，证明了钟控输入与输出序列之间互信息是输出序列长度的严格递增函数，进而对控选逻辑序列设计进行分析。
The sequences of multi-value additive combined generator are analyzed by information theory, and some results are obtained. The mutual information between clock controlled sequence and clock controlled output sequence is zero, and it is proved that the mutual information of clock-controlled input and output sequences is a strictly monotone increasing function of the output sequence length. Furthermore, the design of control-choice cryptographic logic sequences is analyzed.
出处
《信息安全与通信保密》
2009年第8期268-270,275,共4页
Information Security and Communications Privacy
基金
现代通信国家重点实验室基金资助项目（编号：9140C1102030702）.
关键词
多值“加法型”组合生成器
互信息
控选密码逻辑
multi value additive combined generator
mutual information
control-choice cryptographic logic
