摘要
功率MOS管的封装贴片工艺会在贴片层中引入气泡,从而严重降低器件的机械性能、热性能和电学性能。本研究就VDMOS管D-PAK封装模式,给出了贴片工艺中气泡的产生机制及其影响,并利用FEA方法建立了其D-PAK封装的热学模型。根据模拟结果,在贴片层中气泡含量提高时,热阻会急剧增大而降低器件的散热性能。
Die attach process for power MOSFET package will induce voids in the solder layer, it will greatly degrade the mechanical, thermal and electrical performance of device. The formation reasons in die attach process based on the D-PAK for VDMOS were presented. A thermal impedance model was proposed through the FEA （finite element analysis） method, our simulation results show that voids in the solder layer have a detrimental effect on heat flow and increase the thermal impedance of the packaged device.
出处
《半导体技术》
CAS
CSCD
北大核心
2007年第5期436-439,共4页
Semiconductor Technology
基金
国家自然科学基金项目(90607019)
