摘要
首先以序列检测器为例，分析了时序逻辑电路的设计过程，指出求最简状态图是其主要困难之一，并讨论了如何定义最简状态和利用分支图求出状态图的方法其次，讨论了使用计算机辅助设计的可能性，指出采用分支图法可以使计算机求状态图的工作量由无穷高阶降低到二阶。最后指出，分支图法也适用于其他有输入信号的时序逻辑电路的设计。
The design process of sequential logictcircui,which’s one of the major difficulties is to seek the sinplest state transform diagram,and how to define the transform diagram and the method of getting state transform diagram with branch map are discussed by instancing the sequence detector.Then the possibility of using computer aided design is also discussed.The amount of work would reduce from infinite order to 2 order by branch map,using the computer to seek state transform diagram.Finally it is pointed out that branch map method is also saitable for designing other sequential logic circuit which has input signal.
出处
《华东交通大学学报》
1995年第3期44-49,共6页
Journal of East China Jiaotong University
